An All-digital 8.6-nJ/Frame 65-nm Tsetlin Machine Image Classification Accelerator

TL;DR

This paper introduces an energy-efficient, all-digital hardware accelerator for the Tsetlin machine algorithm, enabling fast and accurate image classification in low-power applications.

Contribution

It presents the first dedicated hardware implementation of the Tsetlin machine, demonstrating high classification speed and energy efficiency for image recognition tasks.

Findings

Achieves 60.3k classifications/sec at 8.6 nJ per classification.

Matches software accuracy on MNIST, Fashion-MNIST, Kuzushiji-MNIST datasets.

Occupies 2.7 mm² in 65 nm CMOS technology.

Abstract

We present an all-digital programmable machine learning accelerator chip for image classification, underpinning on the Tsetlin machine (TM) principles. The TM is an emerging machine learning algorithm founded on propositional logic, utilizing sub-pattern recognition expressions called clauses. The accelerator implements the coalesced TM version with convolution, and classifies booleanized images of 28$\times$28 pixels with 10 categories. A configuration with 128 clauses is used in a highly parallel architecture. Fast clause evaluation is achieved by keeping all clause weights and Tsetlin automata (TA) action signals in registers. The chip is implemented in a 65 nm low-leakage CMOS technology, and occupies an active area of 2.7 mm$^2$. At a clock frequency of 27.8 MHz, the accelerator achieves 60.3k classifications per second, and consumes 8.6 nJ per classification. This demonstrates the energy-efficiency of the TM, which was the main motivation for developing this chip. The latency for classifying a single image is 25.4 $\mu$s which includes system timing overhead. The accelerator achieves 97.42%, 84.54% and 82.55% test accuracies for the datasets MNIST, Fashion-MNIST and Kuzushiji-MNIST, respectively, matching the TM software models.