Latch Based Design for Fast Voltage Droop Response

TL;DR

This paper introduces a latch-based, PLL-free voltage droop correction circuit for VLSI systems that responds quickly and simplifies the design by replacing flip-flops with latches, with successful implementation on 130 nm technology.

Contribution

A novel latch-based voltage droop correction circuit that responds within two clock cycles and replaces flip-flops with differential sensors, improving speed and design simplicity.

Findings

Responds within two clock cycles

Halves the length of the synchroniser chain

Successfully implemented on 130 nm process technology

Abstract

We present a latch-based and PLL-free design of the voltage droop correction circuit of Lenzen, Fuegger, Kinali, and Wiederhake\cite{DroopJournal}. Such a circuit dynamically modifies the clock frequency of a digital clock for VLSI systems. Our circuit responds within two clock cycles and halves the length of the synchroniser chain compared to the previous design. Further, we introduce a differential sensor based design for masking latches as a replacement for masking flip flops that the design of \cite{DroopJournal} requires, but leaves unspecified. The use of latches instead of threshold-altered flip flops alters the timing properties of our design and thus the proofs of correctness that accompanied their design require modifications which we present here. This design has been successfully implemented on the IHP 130 nm process technology. The results of the experimental measurements will be discussed in a subsequent publication.