ACiS: Complex Processing in the Switch Fabric

TL;DR

ACiS introduces a comprehensive framework for advanced in-switch processing, enabling flexible, programmable, and fused collective operations in FPGA-augmented network switches to accelerate HPC applications.

Contribution

The paper presents ACiS, a unified taxonomy and hardware/software framework for in-switch processing, expanding capabilities beyond fixed collectives to user-defined, stateful, and fused operations.

Findings

Supports multiple new operation types in switch hardware

Enables programmable in-switch data processing for HPC

Facilitates transparent acceleration of MPI applications

Abstract

For the last three decades a core use of FPGAs has been for processing communication: FPGA-based SmartNICs are in widespread use from the datacenter to IoT. Augmenting switches with FPGAs, however, has been less studied, but has numerous advantages built around the processing being moved from the edge of the network to the center. Communication switches have previously been augmented to process collectives, e.g., IBM BlueGene and Mellanox SHArP, but the support has been limited to a small set of predefined scalar operations and datatypes. Here we present ACiS, a framework and taxonomy for Advanced Computing in the Switch that unifies and expands our previous work in this area. In addition to fixed scalar collectives (Type 1), we propose three more types of in-switch application processing: (Type 2) User-defined operations and types, including data structures; (Type 3) Look-aside operations that have state within the operation and can have loops; and (Type 4) Fused collectives built by fusing multiple existing collectives or collectives with map computations. ACiS is supported in hardware with modular switch extensions including a CGRA architecture. Software support for ACiS includes evaluation and translation of relevant parts of user programs, compilation of user specifications into control flow graphs, and mapping the graphs into switch hardware. The overall goal is the transparent acceleration of HPC applications encapsulated within an MPI implementation.