Chip-to-chip photonic connectivity in multi-accelerator servers for ML

TL;DR

This paper introduces a rack-scale ML architecture utilizing chip-to-chip silicon photonics, achieving faster communication and training throughput in multi-accelerator servers.

Contribution

It presents a novel multi-accelerator server architecture with chip-to-chip photonic connectivity enabling efficient resource sharing and improved ML training performance.

Findings

74% faster collective communication

1.7X increase in training throughput

Effective multi-tenancy with resource slicing

Abstract

We present a rack-scale compute architecture for ML using multi-accelerator servers connected via chip-to-chip silicon photonic components. Our architecture achieves (1) multi-tenanted resource slicing without fragmentation, (2) 74% faster rack-scale collective communication, and (3) 1.7X speedup in end-to-end ML training throughput.