Exploring the Potential of Wireless-enabled Multi-Chip AI Accelerators

TL;DR

This paper investigates how wireless interconnects can enhance multi-chip AI accelerators, demonstrating potential speedups and emphasizing load balancing for improved performance in heterogeneous chip architectures.

Contribution

It introduces the use of wireless technology as a supplement to wired interconnects in multi-chip AI accelerators, showing potential performance benefits.

Findings

Wireless interconnects can improve speed by up to 20%.

Average speedup of 10% observed with wireless integration.

Load balancing between wired and wireless links is crucial.

Abstract

The insatiable appetite of Artificial Intelligence (AI) workloads for computing power is pushing the industry to develop faster and more efficient accelerators. The rigidity of custom hardware, however, conflicts with the need for scalable and versatile architectures capable of catering to the needs of the evolving and heterogeneous pool of Machine Learning (ML) models in the literature. In this context, multi-chiplet architectures assembling multiple (perhaps heterogeneous) accelerators are an appealing option that is unfortunately hindered by the still rigid and inefficient chip-to-chip interconnects. In this paper, we explore the potential of wireless technology as a complement to existing wired interconnects in this multi-chiplet approach. Using an evaluation framework from the state-of-the-art, we show that wireless interconnects can lead to speedups of 10% on average and 20% maximum. We also highlight the importance of load balancing between the wired and wireless interconnects, which will be further explored in future work.