Evaluation of isolation design flow (IDF) for Single Chip Cryptography (SCC) application

TL;DR

This paper evaluates the effectiveness of Xilinx's Isolation Design Flow (IDF) in ensuring reliability of FPGA-based cryptographic applications by fault injection and behavior analysis.

Contribution

It provides an independent assessment of IDF's reliability guarantees through fault injection experiments on AES implementation.

Findings

IDF improves fault tolerance in FPGA cryptography applications.

Fault injection results show IDF's effectiveness in detecting and mitigating faults.

Provides statistical data supporting IDF's reliability claims.

Abstract

Field Programmable Gate Arrays (FPGAs) are increasingly in various applications. This is due to the fact that they provide flexibility to reprogram and modify in realtime with minimum effort. The increasing usage of FPGA must also ensure its end users with a guarantee that they are able to overcome failures and work in the harshest of environments. Today's end user demands a guarantee that the system he/she is buying remains functional. FPGA Vendor Xilinx provides its users with that guarantee in the name of Isolation Design flow or IDF for short. Xilinx claims that IDF can help ensure users reliability while providing flexibility. If true, application that can benefit from IDF are vast, such as Avionics, Unmanned probes, Self-driving fully autonomous vehicles, etc. This thesis puts the Xilinx claim regarding IDF to the test by implementing a single-chip cryptographic application, namely Advanced Encryption Standard, according to the rules and regulations defined by isolation design flow. This thesis does so by replicating and injecting faults in the system that conforms to the rules of IDF and records its behavior firsthand to observe IDF effectiveness. This thesis can also help end users and system evaluators interested in effectiveness of IDF with an independent view other than Xilinx by providing them with statistical data collected to remove all doubts.