Overlay-aware Variation Study of Flip FET and Benchmark with CFET

TL;DR

This study analyzes overlay-induced variations in Flip FETs (FFET) compared to CFETs, showing FFET's robustness in power-performance despite lithography misalignments and identifying key variation sources.

Contribution

It provides a comprehensive overlay-aware variation analysis of FFET, benchmarks it against CFET, and demonstrates methods to mitigate variation effects through design optimization.

Findings

FFET's iso-leakage frequency degrades up to 2.20% at 4 nm misalignment

Drain Merge resistance significantly degrades with increased misalignment

FFET maintains better power-performance than CFET up to 8 nm misalignment

Abstract

In this work, we carried out an overlay-aware variation study on Flip FET (FFET) considering the impact on RC parasitics induced by the lithography misalignment in backside processes, and benchmarked it with CFET in terms of the power-performance (PP) and variation sources. The iso-leakage frequency degrades up to 2.20% with layout misalignment of 4 nm. It's found that the Drain Merge resistance degrades significantly with misalignment increasing and is identified as the major variation source. Through careful DTCO with design rule optimization, the variation can be greatly suppressed, while the resistance fluctuation of the DM also drops substantially. Monte Carlo random experiments were also conducted, validating the variation reduction. Comparing with the CFET featuring self-aligned gate and much less overlay induced misalignment, fortunately, FFET's PP is still better except when misalignment reaches 8 nm, which is out of spec and nearly impossible. Considering the variabilities induced by the high aspect ratio processes, CFET still faces big challenges compared with FFET.