A Benchmarking Platform for DDR4 Memory Performance in Data-Center-Class FPGAs

TL;DR

This paper presents a flexible benchmarking platform for evaluating DDR4 memory performance in data-center-class FPGAs, enabling detailed analysis of memory traffic and access patterns to optimize data exchange.

Contribution

It introduces a configurable, FPGA-based benchmarking platform capable of assessing DDR4 memory performance with complex traffic patterns and multiple channels in data-center environments.

Findings

Effective evaluation of DDR4 memory performance achieved

Platform supports multiple memory channels and data rates

Demonstrated on AMD Kintex UltraScale 115 FPGA

Abstract

FPGAs are increasingly utilized in data centers due to their capacity to exploit data parallelism in computationally intensive workloads. Furthermore, the processing of modern data center workloads requires moving vast amounts of data, making it essential to optimize data exchange between FPGAs and memory. This paper introduces a novel benchmarking platform for the evaluation of DDR4 memory performance in data-center-class FPGAs. The proposed solution features highly configurable traffic generation with complex memory access patterns defined at run time and can be flexibly instantiated on the target FPGA to support multiple memory channels and varying data rates. An extensive experimental campaign, targeting the AMD Kintex UltraScale 115 FPGA and encompassing up to three memory channels with data rates ranging from 1600 to 2400 MT/s and various memory traffic configurations, demonstrates the benchmarking platform's capability to effectively evaluate DDR4 memory performance.