Ion-Trap Chip Architecture Optimized for Implementation of Quantum Error-Correcting Code

TL;DR

This paper introduces a scalable ion-trap chip architecture optimized for quantum error correction, significantly reducing logical error rates and enabling reliable execution of large-scale quantum algorithms.

Contribution

It presents a novel trap design that efficiently integrates quantum error correction with minimal ion shuttling and hardware complexity.

Findings

Increasing code distance reduces logical error probability by two orders of magnitude.

The architecture can reliably support algorithms with thousands of logical qubits.

Logical two-qubit gate error rates as low as 10^{-8} achieved with the proposed design.

Abstract

We propose a scalable trapped-ion quantum-computing architecture that efficiently incorporates quantum error correction. The chip design exploits orthogonal qubit connectivity by assigning horizontal trap regions to transversal logical gates and vertical regions to nontransversal gates and syndrome extraction, thereby enabling universal gate operations with minimal ion shuttling and reduced hardware complexity. Using a dedicated software tool, we evaluate the architecture on several benchmark algorithms and scheduling policies for two-dimensional color code of varying code distance. Our results demonstrate that increasing the code distance by two reduces the effective logical two-qubit gate error probability by approximately two orders of magnitude, reaching values as low as $10^{-8}$ with the $[[31, 1, 7]]$ color code. This improvement substantially expands the range of algorithms that can be executed reliably, up to scales of a few thousand logical qubits, depending on the algorithmic structure. Overall, these findings validate the practicality and scalability of the proposed architecture and its control strategies, highlighting a viable route toward fault-tolerant, trapped-ion quantum computing.