A VM-HDL Co-Simulation Framework for Systems with PCIe-Connected FPGAs

TL;DR

This paper introduces a VM-HDL co-simulation framework that enables efficient development and debugging of PCIe-connected FPGA systems by providing full visibility and reducing debug iteration times.

Contribution

The paper presents a novel co-simulation framework that synchronizes virtual machine, hardware description language, and physical FPGA systems for improved debugging.

Findings

Reduces debug iteration time significantly.

Provides full visibility into FPGA and host software.

Enables accurate simulation of PCIe-connected FPGA systems.

Abstract

PCIe-connected FPGAs are gaining popularity as an accelerator technology in data centers. However, it is challenging to jointly develop and debug host software and FPGA hardware. Changes to the hardware design require a time-consuming FPGA synthesis process, and modification to the software, especially the operating system and device drivers, can frequently cause the system to hang, without providing enough information for debugging. The combination of these problems results in long debug iterations and a slow development process. To overcome these problems, we designed a VM-HDL co-simulation framework, which is capable of running the same software, operating system, and hardware designs as the target physical system, while providing full visibility and significantly shorter debug iterations.