Towards a Cryogenic CMOS-Memristor Neural Decoder for Quantum Error Correction

TL;DR

This paper introduces a cryogenic CMOS-memristor neural decoder ASIC designed for quantum error correction, demonstrating stable operation and power efficiency at cryogenic temperatures down to 1.2K.

Contribution

It presents a novel memristor-based neural decoder architecture optimized for cryogenic environments, enabling scalable quantum error correction hardware.

Findings

Stable activation functions at cryogenic temperatures

Consistent power consumption across temperature ranges

Effective in-memory computing with memristor crossbars

Abstract

This paper presents a novel approach utilizing a scalable neural decoder application-specific integrated circuit (ASIC) based on metal oxide memristors in a 180nm CMOS technology. The ASIC architecture employs in-memory computing with memristor crossbars for efficient vector-matrix multiplications (VMM). The ASIC decoder architecture includes an input layer implemented with a VMM and an analog sigmoid activation function, a recurrent layer with analog memory, and an output layer with a VMM and a threshold activation function. Cryogenic characterization of the ASIC is conducted, demonstrating its performance at both room temperature and cryogenic temperatures down to 1.2K. Results indicate stable activation function shapes and pulse responses at cryogenic temperatures. Moreover, power consumption measurements reveal consistent behavior at room and cryogenic temperatures. Overall, this study lays the foundation for developing efficient and scalable neural decoders for quantum error correction in cryogenic environments.