Parameterized Hardware Architecture for Frame Synchronization at all Noise Levels
Dimitris Nikolaidis

TL;DR
This paper presents a hardware architecture using digital correlation for frame synchronization that is effective across all noise levels, capable of handling large sync words at high data rates with high accuracy.
Contribution
It introduces a minimalistic, FPGA-implementable architecture employing binary sync-word correlation with tree structures for near-perfect synchronization at any noise level.
Findings
Achieves 10e-5 synchronization error at 0.3 bit error rate
Supports sync words larger than 500 bits at over 20 Gbps
Practical implementation on commercial FPGAs
Abstract
Frame synchronization is the act of discerning the first bit of a valid data frame inside an incoming transmission. This is particularly important in high-noise environments where the communication channel significantly alters transmitted signals. Sync word frame synchronization is a subcategory of synchronization methods where sync words are detected through digital correlation. Despite its simplicity, this method has been overlooked in literature in favor of more sophisticated and mathematically more optimal solutions. In this article we employ binary sync-word correlation-based synchronization to achieve near perfect frame synchronization at any noise level. The proposed architecture leverages XNOR gates, adder and comparator tree structures to detect sync words that are placed in front of the frames through digital correlation. The tree structures are circuit elements that mimic…
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Taxonomy
TopicsEmbedded Systems Design Techniques
MethodsSparse Evolutionary Training
