Efficient Synaptic Delay Implementation in Digital Event-Driven AI Accelerators

TL;DR

This paper introduces the Shared Circular Delay Queue (SCDQ), a hardware structure that efficiently implements synaptic delays in digital neuromorphic accelerators, improving memory scalability and energy efficiency for delay-parameterized neural networks.

Contribution

The paper presents SCDQ, a novel hardware design for synaptic delays that scales better in memory and supports co-optimization, advancing neuromorphic accelerator technology.

Findings

SCDQ scales better in memory than existing approaches.

SCDQ improves energy efficiency and latency in neural network inference.

Memory scaling is influenced by model sparsity, not just network size.

Abstract

Synaptic delay parameterization of neural network models have remained largely unexplored but recent literature has been showing promising results, suggesting the delay parameterized models are simpler, smaller, sparser, and thus more energy efficient than similar performing (e.g. task accuracy) non-delay parameterized ones. We introduce Shared Circular Delay Queue (SCDQ), a novel hardware structure for supporting synaptic delays on digital neuromorphic accelerators. Our analysis and hardware results show that it scales better in terms of memory, than current commonly used approaches, and is more amortizable to algorithm-hardware co-optimizations, where in fact, memory scaling is modulated by model sparsity and not merely network size. Next to memory we also report performance on latency area and energy per inference.