HEPPO-GAE: Hardware-Efficient Proximal Policy Optimization with Generalized Advantage Estimation
Hazem Taha, Ameer M. S. Abdelhadi

TL;DR
HEPPO-GAE is an FPGA-based accelerator that significantly improves the efficiency of PPO training by optimizing the GAE computation stage with a novel parallel, pipelined architecture and memory standardization techniques.
Contribution
The paper presents a hardware-efficient FPGA accelerator for GAE in PPO, introducing a standardization and quantization method that reduces memory usage and boosts training speed.
Findings
Achieves 4x reduction in memory usage.
Increases PPO training speed by 30%.
Reduces memory access time significantly.
Abstract
This paper introduces HEPPO-GAE, an FPGA-based accelerator designed to optimize the Generalized Advantage Estimation (GAE) stage in Proximal Policy Optimization (PPO). Unlike previous approaches that focused on trajectory collection and actor-critic updates, HEPPO-GAE addresses GAE's computational demands with a parallel, pipelined architecture implemented on a single System-on-Chip (SoC). This design allows for the adaptation of various hardware accelerators tailored for different PPO phases. A key innovation is our strategic standardization technique, which combines dynamic reward standardization and block standardization for values, followed by 8-bit uniform quantization. This method stabilizes learning, enhances performance, and manages memory bottlenecks, achieving a 4x reduction in memory usage and a 1.5x increase in cumulative rewards. We propose a solution on a single SoC device…
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Taxonomy
TopicsParallel Computing and Optimization Techniques
MethodsSPEED: Separable Pyramidal Pooling EncodEr-Decoder for Real-Time Monocular Depth Estimation on Low-Resource Settings · Entropy Regularization · Proximal Policy Optimization
