Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction

TL;DR

This paper introduces a new hardware abstraction called the position graph for trapped-ion quantum architectures, enabling scalable and efficient compilation methods that outperform existing heuristics in speed.

Contribution

It proposes the position graph abstraction and novel scheduling algorithms SHAPER and SHAW for trapped-ion quantum computers, improving compilation efficiency and scalability.

Findings

Heuristic algorithms are up to 4 times faster than baseline.

The position graph framework effectively models various architectures.

Optimal schedules from linear programming serve as benchmarks.

Abstract

With the growth of quantum platforms for gate-based quantum computation, compilation holds a crucial role in deciding the success of the implementation. While there has been rich research in compilation techniques for the superconducting-qubit regime. The trapped-ion architectures, currently leading in robust quantum computations for their reliable operations, still lack competitive compilation strategies. This work introduces a unifying hardware abstraction, the ``position graph'', representing various hardware architectures. With this abstraction, we model trapped-ion Quantum Charge-Coupled Device (QCCD) architectures, enabling high-quality, scalable compilation methods. Specifically, we propose scheduling algorithms called SHuttling-Aware PERmutative (SHAPER) and SHuttling-AWare (SHAW) heuristic searches to tackle the complex constraints and dynamics of trapped-ion machines, with the cooperation of state-of-the-art permutation-aware mapping. These approaches generate executable circuits and native instructions that respect the physical constraints of shuttling-based architectures. We evaluate proposed algorithms across theorized and real architectures using the position graph framework. For completeness, we also introduce a linear program of trapped-ion scheduling that yields the optimal schedules, enabling a direct comparison with our heuristics. Our algorithm can successfully compile programs for extreme architectures where priori algorithms fail. When the baseline does complete, our produced schedules are $1.45$ times faster on average, with best-case speedups up to $4$ times faster.