A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform

TL;DR

This paper introduces a fully pipelined FPGA hardware architecture for polynomial multiplication using NTT, significantly reducing processing time and resource usage compared to existing solutions, with applications in modern encryption schemes.

Contribution

It proposes a novel FIFO-based pipelined hardware design for NTT-based polynomial multiplication that improves speed and resource efficiency.

Findings

Achieves two-fold reduction in processing time.

Uses fewer resources than existing fastest solutions.

Enables twice as much encryption processing in the same time.

Abstract

This paper presents digital hardware for computing polynomial multiplication using Number Theoretic Transform (NTT), specifically designed for implementation on Field Programmable Gate Arrays (FPGAs). Multiplying two large polynomials applies to many modern encryption schemes, including those based on Ring Learning with Error (RLWE). The proposed design uses First In, First Out (FIFO) buffers to make the design fully pipelined and capable of computing two n degree polynomials in n/2 clock cycles. This hardware proposes a two-fold reduction in the processing time of polynomial multiplication compared to state-of-the-art enabling twice as much encryption in the same amount of time. Despite that, the proposed hardware utilizes fewer resources than the fastest-reported work.