SALSA: a new versatile readout chip for MPGD detectors

D. Neyret (1); P. Baron (1); F. Bouyjou (1); M. Bregant (2); S. Chevobbe (1); Y. Degerli (1); C. Flouzat (1); O. Gevin (1); F. Guilloux (1); H. Hernandez (6); I. Mandjavidze (1); M. Munhoz (2); B. Sanches (3); L. Severo (5); J.N. Soares (4); W. Van Noije (3); and F. William da Costa (3) ((1) CEA IRFU; Universit\'e Paris-Saclay; (2) Instituto de F\'isica da Universidade de S\~ao Paulo; (3) Escola Polit\'ecnica da Universidade de S\~ao Paulo; (4) Escola de Engenharia de S\~ao Carlos; Universidade de S\~ao Paulo; (5) Divis\~ao Engenharia Eletr\^onica; Instituto Tecnol\'ogico de Aeron\'autica; (6) TID Instrumentation Division; Integrated Circuits Department; SLAC; Stanford University)

arXiv:2501.10237·physics.ins-det·June 26, 2025

SALSA: a new versatile readout chip for MPGD detectors

D. Neyret (1), P. Baron (1), F. Bouyjou (1), M. Bregant (2), S. Chevobbe (1), Y. Degerli (1), C. Flouzat (1), O. Gevin (1), F. Guilloux (1), H. Hernandez (6), I. Mandjavidze (1), M. Munhoz (2), B. Sanches (3), L. Severo (5), J.N. Soares (4), W. Van Noije (3)

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TL;DR

The SALSA chip is a versatile, integrated readout ASIC designed for MPGD detectors, adaptable for various applications like TPC and photon detection, with prototypes developed for future deployment in the EPIC experiment.

Contribution

It introduces a new adaptable readout ASIC with integrated processing for MPGD detectors, supporting both continuous and triggered readout modes.

Findings

01

Prototype blocks tested successfully

02

Next prototype under development for 2025

03

Final production planned for 2027

Abstract

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. The final prototype will be…

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Taxonomy

TopicsCCD and CMOS Imaging Sensors · Particle Detector Development and Performance