Hybrid Parallel Collaborative Simulation Framework Integrating Device Physics with Circuit Dynamics for PDAE-Modeled Power Electronic Equipment

TL;DR

This paper introduces a hybrid parallel simulation framework that integrates device physics with circuit dynamics to enable fast, accurate PDAE-based power electronic equipment analysis, significantly improving computational efficiency for complex multiscale simulations.

Contribution

It presents a novel hybrid-parallel collaborative framework that efficiently solves coupled PDAEs in power electronics, enabling high-speed, physics-based simulations of multiple devices simultaneously.

Findings

Achieves up to 60x faster simulation speed compared to commercial software.

Maintains carrier-level accuracy in complex device and circuit simulations.

Effectively handles multiscale, nonlinear PDAE systems in power electronics.

Abstract

Optimizing high-performance power electronic equipment, such as power converters, requires multiscale simulations that incorporate the physics of power semiconductor devices and the dynamics of other circuit components, especially in conducting Design of Experiments (DoEs), defining the safe operating area of devices, and analyzing failures related to semiconductor devices. However, current methodologies either overlook the intricacies of device physics or do not achieve satisfactory computational speeds. To bridge this gap, this paper proposes a Hybrid-Parallel Collaborative (HPC) framework specifically designed to analyze the Partial Differential Algebraic Equation (PDAE) modeled power electronic equipment, integrating the device physics and circuit dynamics. The HPC framework employs a dynamic iteration to tackle the challenges inherent in solving the coupled nonlinear PDAE system, and utilizes a hybrid-parallel computing strategy to reduce computing time. Physics-based system partitioning along with hybrid-process-thread parallelization on shared and distributed memory are employed, facilitating the simulation of hundreds of partial differential equations (PDEs)-modeled devices simultaneously without compromising speed. Experiments based on the hybrid line commutated converter and reverse-blocking integrated gate-commutated thyristors are conducted under 3 typical real-world scenarios: semiconductor device optimization for the converter; converter design optimization; and device failure analysis. The HPC framework delivers simulation speed up to 60 times faster than the leading commercial software, while maintaining carrier-level accuracy in the experiments. This shows great potential for comprehensive analysis and collaborative optimization of devices and electronic power equipment, particularly in extreme conditions and failure scenarios.