Scheduling Coflows for Minimizing the Maximum Completion Time in Heterogeneous Parallel Networks

TL;DR

This paper presents a polynomial-time approximation algorithm for coflow scheduling in heterogeneous parallel networks, aiming to minimize maximum completion time with proven guarantees across various switch architectures.

Contribution

It introduces a novel approximation algorithm tailored for different switch architectures in heterogeneous networks, addressing the NP-hard coflow scheduling problem.

Findings

Achieves an approximation guarantee of min{τ, 2Nm+1} for EPS switches.

Guarantees a 2-approximation in environments with not-all-stop OCS.

Provides a 2τ+2 approximation for all-stop OCS setups.

Abstract

Coflow is a prominent network abstraction for modeling communication patterns in data centers. Since coflow scheduling in large-scale data centers is $\mathcal{NP}$-hard, this paper investigates this problem within heterogeneous parallel networks featuring multiple network cores. We propose a polynomial-time approximation algorithm to minimize the makespan (maximum completion time). We consider three distinct switch architectures: Electronic Packet Switches (EPS), not-all-stop Optical Circuit Switches (OCS), and all-stop OCS. Under a deployment where all switches are EPS, the proposed algorithm achieves an approximation guarantee of $\min\left\{\tau, 2Nm+1\right\}$, which reduces to $2$ when $m=2$ where $\tau$ is the maximum number of flows of each port of switch, $N$ is the number of input/output ports and $m$ is the number of network cores. In environments entirely composed of not-all-stop OCS, the algorithm guarantees an approximation ratio of $2\min\left\{\tau, 2Nm+1\right\}$, and $4$ when $m=2$. For setups consisting solely of all-stop OCS, the approximation guarantee becomes $2\min\left\{2\tau-1, 2Nm+\tau\right\}$, and $2\tau+2$ when $m=2$. Furthermore, in a hybrid network architecture, we show that the overall performance guarantee of our algorithm is dominated by the least performant switch architecture in the system.