Holistic Optimization Framework for FPGA Accelerators

TL;DR

Prometheus is a comprehensive FPGA optimization framework that automates the design process by integrating multiple transformations and leveraging NLP techniques to maximize performance and resource efficiency.

Contribution

It introduces a unified optimization approach that considers interdependent transformations and resource constraints, improving FPGA design automation and QoR.

Findings

Outperforms existing FPGA optimization frameworks in benchmarks.

Effectively balances computation and memory access for better performance.

Reduces manual tuning through automated, holistic optimization.

Abstract

Customized accelerators have revolutionized modern computing by delivering substantial gains in energy efficiency and performance through hardware specialization. Field-Programmable Gate Arrays (FPGAs) play a crucial role in this paradigm, offering unparalleled flexibility and high-performance potential. High-Level Synthesis (HLS) and source-to-source compilers have simplified FPGA development by translating high-level programming languages into hardware descriptions enriched with directives. However, achieving high Quality of Results (QoR) remains a significant challenge, requiring intricate code transformations, strategic directive placement, and optimized data communication. This paper presents Prometheus, a holistic optimization framework that integrates key optimizations -- including task fusion, tiling, loop permutation, computation-communication overlap, and concurrent task execution -- into a unified design space. By leveraging Non-Linear Programming (NLP) methodologies, Prometheus explores the optimization space under strict resource constraints, enabling automatic bitstream generation. Unlike existing frameworks, Prometheus considers interdependent transformations and dynamically balances computation and memory access. We evaluate Prometheus across multiple benchmarks, demonstrating its ability to maximize parallelism, minimize execution stalls, and optimize data movement. The results showcase its superior performance compared to state-of-the-art FPGA optimization frameworks, highlighting its effectiveness in delivering high QoR while reducing manual tuning efforts.