LUCAS: A Low-Power Ultra-Low Jitter Compact ASIC for SiPM Targetting ToF-CT

TL;DR

LUCAS is a compact, low-power ASIC designed for SiPMs that achieves ultra-low jitter and high bandwidth, suitable for fast timing in ToF-CT applications, with promising simulation results for sub-40 ps jitter.

Contribution

This paper introduces LUCAS, a novel low-power ASIC with ultra-low jitter and high bandwidth tailored for SiPM-based ToF-CT systems, featuring a compact design and promising simulation outcomes.

Findings

Predicted less than 40 ps FWHM SPTR jitter from simulations.

Power consumption of approximately 3.2 mW per channel.

High bandwidth of 3.9 GHz for fast timing applications.

Abstract

We present LUCAS (Low power Ultra-low jitter Compact ASIC for SiPM), an analog front-end for Silicon Photomultipliers (SiPM) targeting fast timing detectors in Time-of-Flight Computed Tomography (ToF-CT). LUCAS features a very low input impedance preamplifier followed by a voltage comparator. It is designed in TSMC 65 nm low-power CMOS technology with a power supply of 1.2 V. Our first 8-channel prototype has been sent to fabrication and will be received in August 2023. Post-layout simulations predict less than 40 ps FWHM SPTR jitter and an approximate power consumption of 3.2 mW per channel. The front end is suitable for applications with rigorous jitter requirements and high event rates, thanks to its 3.9 GHz unity-gain bandwidth. The front-end compact form factor will facilitate its incorporation into systems demanding high channel densities.