Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories

TL;DR

This paper introduces a monolithic 3D FPGA architecture using BEOL transistors with AOS technology, achieving significant improvements in area, latency, and power efficiency for reconfigurable circuits.

Contribution

It presents a novel M3D FPGA design that integrates BEOL AOS transistors for configuration memory, reducing overhead and latency compared to traditional approaches.

Findings

3.4x lower area-time squared product (AT^2)

27% lower critical path latency

26% lower routing block power

Abstract

This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power efficiency. By integrating n-type (W-doped In_2O_3) and p-type (SnO) amorphous oxide semiconductor (AOS) transistors in the BEOL, Si SRAM configuration bits are substituted with a less leaky equivalent that can be programmed at logic-compatible voltages. BEOL-compatible AOS transistors are currently under extensive research and development in the device community, with investment by leading foundries, from which reported data is used to develop robust physics-based models in TCAD that enable circuit design. The use of AOS pass gates reduces the overhead of reconfigurable circuits by mapping FPGA switch block (SB) and connection block (CB) matrices above configurable logic blocks (CLBs), thereby increasing the proximity of logic elements and reducing latency. By interfacing with the latest Verilog-to-Routing (VTR) suite, an AOS-based M3D FPGA design implemented in 7 nm technology is demonstrated with 3.4x lower area-time squared product (AT^2), 27% lower critical path latency, and 26% lower reconfigurable routing block power on benchmarks including hyperdimensional computing and large language models (LLMs).