TransPlace: Transferable Circuit Global Placement via Graph Neural Network

TL;DR

TransPlace is a novel graph neural network-based framework that learns transferable knowledge for global circuit placement, significantly improving efficiency and performance across unseen chip designs.

Contribution

It introduces a graph neural network architecture with new encoding strategies for transferable placement knowledge, enabling faster and better placement of unseen circuits.

Findings

1. TransPlace achieves 1.2x speedup over state-of-the-art methods.

2. It reduces congestion by 30% and timing by 9%.

3. It decreases wirelength by 5%.

Abstract

Global placement, a critical step in designing the physical layout of computer chips, is essential to optimize chip performance. Prior global placement methods optimize each circuit design individually from scratch. Their neglect of transferable knowledge limits solution efficiency and chip performance as circuit complexity drastically increases. This study presents TransPlace, a global placement framework that learns to place millions of mixed-size cells in continuous space. TransPlace introduces i) Netlist Graph to efficiently model netlist topology, ii) Cell-flow and relative position encoding to learn SE(2)-invariant representation, iii) a tailored graph neural network architecture for informed parameterization of placement knowledge, and iv) a two-stage strategy for coarse-to-fine placement. Compared to state-of-the-art placement methods, TransPlace-trained on a few high-quality placements-can place unseen circuits with 1.2x speedup while reducing congestion by 30%, timing by 9%, and wirelength by 5%.