A 65 nm Bayesian Neural Network Accelerator with 360 fJ/Sample In-Word GRNG for AI Uncertainty Estimation

TL;DR

This paper introduces a 65 nm ASIC with integrated Gaussian RNG in SRAM that accelerates Bayesian neural networks for uncertainty estimation, achieving high throughput and low energy consumption suitable for edge AI applications.

Contribution

It presents a novel ASIC design integrating Gaussian RNG directly into SRAM to enable efficient compute-in-memory Bayesian neural network acceleration.

Findings

Achieves 5.12 GSa/s RNG throughput

Reaches 102 GOp/s neural network throughput

Consumes 360 fJ per sample for RNG

Abstract

Uncertainty estimation is an indispensable capability for AI-enabled, safety-critical applications, e.g. autonomous vehicles or medical diagnosis. Bayesian neural networks (BNNs) use Bayesian statistics to provide both classification predictions and uncertainty estimation, but they suffer from high computational overhead associated with random number generation and repeated sample iterations. Furthermore, BNNs are not immediately amenable to acceleration through compute-in-memory architectures due to the frequent memory writes necessary after each RNG operation. To address these challenges, we present an ASIC that integrates 360 fJ/Sample Gaussian RNG directly into the SRAM memory words. This integration reduces RNG overhead and enables fully-parallel compute-in-memory operations for BNNs. The prototype chip achieves 5.12 GSa/s RNG throughput and 102 GOp/s neural network throughput while occupying 0.45 mm2, bringing AI uncertainty estimation to edge computation.