Characterization of Flux Trapping in and Fabrication of Large-Scale Superconductor Circuits Using AC-Biased Shift Registers With 108500 Josephson Junctions

TL;DR

This study characterizes flux trapping and fabrication quality in large-scale superconductor circuits with over 108,000 Josephson junctions, demonstrating effective design strategies and identifying defect rates through extensive testing of flux trapping phenomena.

Contribution

It provides a comprehensive analysis of flux trapping effects, fabrication yield, and parameter spread in large superconductor circuits with innovative moat and ground plane configurations.

Findings

Moats effectively prevent flux trapping outside of them.

Circuits with slit-type moats are fully operational in all cooldowns.

Critical ground plane spacing of 0.6 μm affects flux trapping and circuit operability.

Abstract

A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to ~1.2 $\mu$T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-$\mu$m-wide slit moats occupying <2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t$_c$=0.6 $\mu$m, between them. The presence of GPs spaced below t$_c$ rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.