Harnessing Hardware Acceleration in High-Energy Physics through High-Level Synthesis Techniques
Pelayo Leguina L\'opez, Santiago Folgueras

TL;DR
This paper explores how High-Level Synthesis (HLS) can be used to implement hardware acceleration for high-energy physics data analysis, significantly improving processing speeds and enabling real-time analysis at the Large Hadron Collider.
Contribution
It demonstrates the application of HLS techniques to translate complex physics algorithms into FPGA hardware, optimizing performance for particle detection and reconstruction tasks.
Findings
HLS enables high-speed, low-latency hardware implementations of physics algorithms.
Parallel processing and pipelining in HLS improve computational efficiency.
Case study shows real-time muon track reconstruction using FPGA acceleration.
Abstract
At the Large Hadron Collider, the vast amount of data from experiments demands not only sophisticated algorithms but also substantial computational power for efficient processing. This paper introduces hardware acceleration as an essential advancement for high-energy physics data analysis, focusing specifically on the application of High-Level Synthesis (HLS) to bridge the gap between complex software algorithms and their hardware implementation. We will explore how HLS facilitates the direct implementation of software algorithms into hardware platforms such as FPGAs, enhancing processing speeds and enabling real-time data analysis. This will be highlighted through the case study of a track-finding algorithm for muon reconstruction with the CMS experiment, demonstrating HLS's role in translating computational tasks into high-speed, low-latency hardware solutions for particle detection…
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Taxonomy
TopicsParticle Detector Development and Performance · Parallel Computing and Optimization Techniques · Embedded Systems Design Techniques
