Aligning Netlist to Source Code using SynAlign

TL;DR

SynAlign automates the alignment of netlists to source code in chip design, preserving source correlation across multiple tools and tolerating significant net modifications to improve design efficiency.

Contribution

The paper introduces SynAlign, a novel method for automatic netlist-to-source code alignment that maintains accuracy despite substantial netlist changes.

Findings

SynAlign can tolerate up to 61% net changes without losing alignment accuracy.

It automates the alignment process, reducing manual effort and iterative design overhead.

Enhances chip design workflows by maintaining source correlation across different tools.

Abstract

In current chip design processes, using multiple tools to obtain a gate-level netlist often results in the loss of source code correlation. SynAlign addresses this challenge by automating the alignment process, simplifying iterative design, reducing overhead, and maintaining correlation across various tools. This enhances the efficiency and effectiveness of chip design workflows. Improving characteristics such as frequency through iterative design is essential for enhancing accelerators and chip designs. While synthesis tools produce netlists with critical path information, designers often lack the tools to trace these netlist cells back to their original source code. Mapping netlist components to source code provides early feedback on timing and power for frontend designers. SynAlign automatically aligns post-optimized netlists with the original source code without altering compilers or synthesis processes. Its alignment strategy relies on the consistent design structure throughout the chip design cycle, even with changes in compiler flow. This consistency allows engineers to maintain a correlation between modified designs and the original source code across various tools. Remarkably, SynAlign can tolerate up to 61\% design net changes without impacting alignment accuracy.