A Novel FPGA-based CNN Hardware Accelerator: Optimization for Convolutional Layers using Karatsuba Ofman Multiplier

TL;DR

This paper introduces an FPGA-based CNN hardware accelerator optimized for convolutional layers using the Karatsuba-Ofman multiplier, enhancing speed and resource efficiency in deep learning applications.

Contribution

It presents a novel FPGA architecture for CNN acceleration that integrates the Karatsuba-Ofman multiplier to improve convolution efficiency.

Findings

Enhanced multiplication speed with less hardware resources

Effective implementation on FPGA for AlexNet, VGG16, VGG19

Potential for improved CNN processing performance

Abstract

A new architecture of CNN hardware accelerator is presented. Convolutional Neural Networks (CNNs) are a subclass of neural networks that have demonstrated outstanding performance in a variety of computer vision applications, including object detection, image classification, and many more.Convolution, a mathematical operation that consists of multiplying, shifting and adding a set of input values by a set of learnable parameters known as filters or kernels, which is the fundamental component of a CNN.The Karatsuba Ofman multiplier is known for its ability to perform high-speed multiplication with less hardware resources compared to traditional multipliers. This article examines the usage of the Karatsuba Ofman Multiplier method on FPGA in the prominent CNN designs AlexNet, VGG16, and VGG19.