Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience

TL;DR

This paper discusses the development and open-source release of heterogeneous AI acceleration SoCs within the PULP platform, highlighting architecture, design, verification, and deployment aspects for low-power AI applications.

Contribution

It presents the comprehensive experience of designing heterogeneous AI acceleration SoCs, including architecture, integration, and software development, as a detailed case study.

Findings

Successful open-source release of diverse PULP hardware IPs

Development of efficient AI acceleration SoCs

Integration of hardware and software for AI deployment

Abstract

Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor cores to network-on-chips, peripherals, SoC templates, and full hardware accelerators. In this article, we focus on the PULP experience designing heterogeneous AI acceleration SoCs - an endeavour encompassing SoC architecture definition; development, verification, and integration of acceleration IPs; front- and back-end VLSI design; testing; development of AI deployment software.