A Fully Hardware Implemented Accelerator Design in ReRAM Analog Computing without ADCs

TL;DR

This paper presents a fully hardware-implemented ReRAM-based accelerator that efficiently computes neural networks by eliminating ADCs and DACs, leveraging stochastic binarization and noise sampling for activation functions.

Contribution

It introduces a novel ReRAM-based accelerator design that removes ADCs/DACs and uses stochastic noise for activation functions, enhancing energy and area efficiency.

Findings

Outperforms traditional architectures in all performance metrics

Maintains inference accuracy with the new design

Reduces energy and area overhead significantly

Abstract

Emerging ReRAM-based accelerators process neural networks via analog Computing-in-Memory (CiM) for ultra-high energy efficiency. However, significant overhead in peripheral circuits and complex nonlinear activation modes constrain system energy efficiency improvements. This work explores the hardware implementation of the Sigmoid and SoftMax activation functions of neural networks with stochastically binarized neurons by utilizing sampled noise signals from ReRAM devices to achieve a stochastic effect. We propose a complete ReRAM-based Analog Computing Accelerator (RACA) that accelerates neural network computation by leveraging stochastically binarized neurons in combination with ReRAM crossbars. The novel circuit design removes significant sources of energy/area efficiency degradation, i.e., the Digital-to-Analog and Analog-to-Digital Converters (DACs and ADCs) as well as the components to explicitly calculate the activation functions. Experimental results show that our proposed design outperforms traditional architectures across all overall performance metrics without compromising inference accuracy.