A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA

TL;DR

This paper presents a 64-channel FPGA-based TDC with an average RMS precision of 4.77 ps, utilizing TDL and WU-A techniques, and introduces an online processing scheme to mitigate clock skew issues.

Contribution

The paper introduces a high-precision 64-channel TDC implemented in a 28 nm FPGA with novel online processing for bubble issue mitigation.

Findings

Achieved an average RMS time resolution of 4.77 ps across 64 channels.

Implemented a 28 nm FPGA-based TDC with 3 ps LSB resolution.

Developed an online processing scheme to address clock skew-induced bubbles.

Abstract

We have developed a Time-to-Digital Converter (TDC) application in a Xilinx Kintex-7 Field Programmable Gate Array (FPGA). This TDC, based on the Tapped-Delay Line (TDL) and Wave Union A (WU-A) techniques, achieves an independent time measurement on 32-channel rising edges and 32-channel falling edges. The average time resolution or the Least Significant Bit (LSB) of the 64 channels is measured to be 3 ps level, with an average root mean square (RMS) precision of 4.77 ps, and a maximum RMS below 8 ps. We also propose an online processing scheme that handles the bubble issues caused by clock region skew.