A Time Optimization Framework for the Implementation of Robust and Low-latency Quantum Circuits
Eduardo Willwock Lussi, Rafael de Santiago, Eduardo Inacio Duzzioni

TL;DR
This paper presents a time-optimization framework for quantum circuits that balances fast and robust gates, reducing overall latency and improving success probability, thereby enhancing quantum hardware performance.
Contribution
It introduces a novel pulse scheduling approach that optimally combines fast and robust quantum gates within the same circuit without increasing latency.
Findings
Improves success probability by over 25% on IBMQ Brisbane.
Scales performance gains with increasing qubit count.
Effectively balances gate speed and robustness in quantum circuits.
Abstract
Quantum computing has garnered attention for its potential to solve complex computational problems with considerable speedup. Despite notable advancements in the field, achieving meaningful scalability and noise control in quantum hardware remains challenging. Incoherent errors caused by decoherence restrict the total computation time, making it very short. While hardware advancements continue to progress, quantum software specialists seek to minimize quantum circuit latency to mitigate dissipation. However, at the pulse level, fast quantum gates often lead to leakage, leaving minimal room for further optimization. Recent advancements have shown the effectiveness of quantum control techniques in generating quantum gates robust to coherent error sources. Nevertheless, these techniques come with a trade-off -- extended gate durations. In this paper, we introduce an alternative pulse…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography · Low-power high-performance VLSI design
