Short two-qubit pulse sequences for exchange-only spin qubits in 2D layouts

TL;DR

This paper develops optimized two-qubit pulse sequences for exchange-only spin qubits in 2D quantum dot layouts, analyzing topology effects, reducing sequence lengths, and verifying sequences experimentally to inform scalable quantum hardware design.

Contribution

It introduces a fast optimization method to generate complete pulse sequences for various two-qubit gates across 450 topologies, with experimental validation and architectural insights.

Findings

Sequence length reduced by up to 43% across topologies

Relaxing spin location constraints further reduces sequence length

Experimental verification confirms pulse sequence effectiveness

Abstract

Exchange-only (EO) spin qubits in quantum dots offer an expansive design landscape for architecting scalable device layouts. The study of two-EO-qubit operations, which involve six electrons in six quantum dots, has so far been limited to a small number of the possible configurations, and previous works lack analyses of design considerations and implications for quantum error correction. Using a simple and fast optimization method, we generate complete pulse sequences for CX, CZ, iSWAP, leakage-controlled CX, and leakage-controlled CZ two-qubit gates on 450 unique planar six-dot topologies and analyze differences in sequence length (up to 43\% reduction) across topology classes. In addition, we show that relaxing constraints on post-operation spin locations can yield further reductions in sequence length; conversely, constraining these locations in a particular way generates a CXSWAP operation with minimal additional cost over a standard CX. We integrate this pulse library into the Intel quantum stack and experimentally verify pulse sequences on a Tunnel Falls chip for different operations in a linear-connectivity device to confirm that they work as expected. Finally, we explore architectural implications of these results for quantum error correction. Our work guides hardware and software design choices for future implementations of scalable quantum dot architectures.