Thermal circuit model for silicon quantum-dot array structures

TL;DR

This paper introduces a thermal circuit model for silicon quantum-dot arrays to predict heating effects, validated by experiments, aiding thermal management in large-scale quantum computers.

Contribution

A simple, scalable thermal circuit model for silicon QD arrays is proposed and validated, enabling improved thermal design for quantum computing hardware.

Findings

Model accurately reproduces experimental electron temperature measurements.

Thermal transmission line representation captures heat distribution in QD arrays.

Model facilitates thermal management strategies for large-scale quantum computers.

Abstract

Temperature rise of qubits due to heating is a critical issue in large-scale quantum computers based on quantum-dot (QD) arrays. This leads to shorter coherence times, induced readout errors, and increased charge noise. Here, we propose a simple thermal circuit model to describe the heating effect on silicon QD array structures. Noting that the QD array is a periodic structure, we represent it as a thermal distributed-element circuit, forming a thermal transmission line. We validate this model by measuring the electron temperature in a QD array device using Coulomb blockade thermometry, finding that the model effectively reproduces experimental results. This simple and scalable model can be used to develop the thermal design of large-scale silicon-based quantum computers.