Compressed Sensing Based Residual Recovery Algorithms and Hardware for Modulo Sampling

TL;DR

This paper introduces a novel LASSO-based residual recovery algorithm for modulo sampling in ADCs, improving robustness and speed, and proposes a bits distribution mechanism to enhance practical hardware implementation.

Contribution

It presents LASSO-B2R2, a fast, robust residual recovery algorithm for modulo sampling, and introduces a bits distribution mechanism for efficient hardware realization.

Findings

LASSO-B2R2 outperforms prior methods in speed and robustness.

The bits distribution mechanism improves computational efficiency.

Hardware prototype successfully captures 1-bit folding information.

Abstract

Analog-to-Digital Converters (ADCs) are essential components in modern data acquisition systems. A key design challenge is accommodating high dynamic range (DR) input signals without clipping. Existing solutions, such as oversampling, automatic gain control (AGC), and compander-based methods, have limitations in handling high-DR signals. Recently, the Unlimited Sampling Framework (USF) has emerged as a promising alternative. It uses a non-linear modulo operator to map high-DR signals within the ADC range. Existing recovery algorithms, such as higher-order differences (HODs), prediction-based methods, and beyond bandwidth residual recovery (B2R2), have shown potential but are either noise-sensitive, require high sampling rates, or are computationally intensive. To address these challenges, we propose LASSO-B2R2, a fast and robust recovery algorithm. Specifically, we demonstrate that the first-order difference of the residual (the difference between the folded and original samples) is sparse, and we derive an upper bound on its sparsity. This insight allows us to formulate the recovery as a sparse signal reconstruction problem using the least absolute shrinkage and selection operator (LASSO). Numerical simulations show that LASSO-B2R2 outperforms prior methods in terms of speed and robustness, though it requires a higher sampling rate at lower DR. To overcome this, we introduce the bits distribution mechanism, which allocates 1 bit from the total bit budget to identify modulo folding events. This reduces the recovery problem to a simple pseudo-inverse computation, significantly enhancing computational efficiency. Finally, we validate our approach through numerical simulations and a hardware prototype that captures 1-bit folding information, demonstrating its practical feasibility.