Vertically Integrated Dual-memtransistor Enabled Reconfigurable Heterosynaptic Sensorimotor Networks and In-memory Neuromorphic Computing
Srilagna Sahoo, Abin Varghese, Aniket Sadashiva, Mayank Goyal,, Jayatika Sakhuja, Debanjan Bhowmik, Saurabh Lodha

TL;DR
This paper introduces a vertically integrated dual-memtransistor architecture that enables reconfigurable heterosynaptic sensorimotor networks and in-memory neuromorphic computing with high efficiency and biological plausibility.
Contribution
It presents a novel compact VSFET device combining ferroelectric and non-ferroelectric 2D materials for neuromorphic applications, demonstrating complex synaptic behaviors and logic reconfigurability.
Findings
Emulation of homosynaptic plasticity with high accuracy
Realization of heterosynaptic cooperation and competition behaviors
Logic reconfigurability for Boolean gates
Abstract
Neuromorphic in-memory computing requires area-efficient architecture for seamless and low latency parallel processing of large volumes of data. Here, we report a compact, vertically integrated/stratified field-effect transistor (VSFET) consisting of a 2D non-ferroelectric MoS FET channel stacked on a 2D ferroelectric InSe FET channel. Electrostatic coupling between the ferroelectric and non-ferroelectric semiconducting channels results in hysteretic transfer and output characteristics of both FETs. The gate-controlled MoS memtransistor is shown to emulate homosynaptic plasticity behavior with low nonlinearity, low epoch, and high accuracy supervised (ANN - artificial neural network) and unsupervised (SNN - spiking neural network) on-chip learning. Further, simultaneous measurements of the MoS and InSe transistor synapses help realize complex heterosynaptic…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Ferroelectric and Negative Capacitance Devices · Neural Networks and Reservoir Computing
