The Reliability Issue in ReRam-based CIM Architecture for SNN: A Survey

TL;DR

This survey reviews the reliability challenges in ReRAM-based CIM architectures for SNNs, highlighting device variations and errors, and discusses potential solutions to improve robustness in energy-efficient neuromorphic computing.

Contribution

It provides a comprehensive overview of reliability issues in ReRAM-based CIM for SNNs and summarizes current mitigation strategies, filling a gap in existing literature.

Findings

Device-level variations significantly impact ReRAM reliability.

Operational errors in ReRAM affect SNN performance.

Existing solutions offer partial mitigation of reliability issues.

Abstract

The increasing complexity and energy demands of deep learning models have highlighted the limitations of traditional computing architectures, especially for edge devices with constrained resources. Spiking Neural Networks (SNNs) offer a promising alternative by mimicking biological neural networks, enabling energy-efficient computation through event-driven processing and temporal encoding. Concurrently, emerging hardware technologies like Resistive Random Access Memory (ReRAM) and Compute-in-Memory (CIM) architectures aim to overcome the Von Neumann bottleneck by integrating storage and computation. This survey explores the intersection of SNNs and ReRAM-based CIM architectures, focusing on the reliability challenges that arise from device-level variations and operational errors. We review the fundamental principles of SNNs and ReRAM crossbar arrays, discuss the inherent reliability issues in both technologies, and summarize existing solutions to mitigate these challenges.