AiEDA: Agentic AI Design Framework for Digital ASIC System Design

TL;DR

AiEDA is a novel agentic AI framework that automates and streamlines digital ASIC system design, from concept to layout, using autonomous AI agents to improve efficiency and reduce costs.

Contribution

The paper introduces AiEDA, an innovative agentic design flow that leverages autonomous AI agents for efficient digital ASIC design automation.

Findings

Successful design of an ultra-low-power ASIC for KWS

Automated transition from conceptual design to GDSII layout

Enhanced design efficiency through AI-driven workflows

Abstract

The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design.