Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning
Zhaoying Li, Pranav Dangi, Chenyang Yin, Thilini Kaushalya Bandara,, Rohan Juneja, Cheng Tan, Zhenyu Bai, Tulika Mitra

TL;DR
This paper introduces Plaid, a CGRA architecture and compiler that align compute and communication to significantly improve energy and area efficiency while maintaining performance and generality.
Contribution
The paper presents a novel CGRA design and compiler that leverage recurring communication motifs for more efficient compute-communication provisioning.
Findings
43% reduction in power consumption
46% area savings over baseline CGRA
1.4x performance improvement with similar power
Abstract
Coarse-grained Reconfigurable Arrays (CGRAs) are domain-agnostic accelerators that enhance the energy efficiency of resource-constrained edge devices. The CGRA landscape is diverse, exhibiting trade-offs between performance, efficiency, and architectural specialization. However, CGRAs often overprovision communication resources relative to their modest computing capabilities. This occurs because the theoretically provisioned programmability for CGRAs often proves superfluous in practical implementations. In this paper, we propose Plaid, a novel CGRA architecture and compiler that aligns compute and communication capabilities, thereby significantly improving energy and area efficiency while preserving its generality and performance. We demonstrate that the dataflow graph, representing the target application, can be decomposed into smaller, recurring communication patterns called…
Peer Reviews
No public reviews on file for this paper yet. If you reviewed it on a platform where reviews are public (OpenReview, ICLR, NeurIPS, ICML), you can paste yours below so the community can read it here.
Videos
No videos yet. Explain this paper in a talk, walkthrough, or lecture? Add one.
