A reconfigurable calibration-free digital-to-time converter based on a high-speed transceiver

TL;DR

This paper introduces a reconfigurable, calibration-free digital-to-time converter leveraging high-speed transceivers and real-time decoding, achieving high precision and flexibility for diverse timing applications.

Contribution

It presents a novel high-speed transceiver-based DTC with reconfigurable resolution, real-time decoding, and multifunctionality, validated on FPGA with high accuracy.

Findings

Achieves 100 ps resolution and wide dynamic range from 1 ns to 40 μs.

Demonstrates high stability and calibration-free operation.

Validates effectiveness through FPGA implementation.

Abstract

This paper proposes a high-speed transceiver-based method for implementing a digital-to-time converter (DTC). A real-time decoding technique is introduced to inject time information into high-speed pattern data. The stability of the high-speed clock ensures the high precision of the synthesized timing signal without the need for calibration. The reconfigurability of the clock resources provides the DTC with variable resolution and enhanced flexibility for various applications. Based on this approach, a multifunctional DTC is designed to offer both timing sequence and random timing signal functionalities, catering to a wide range of application scenarios. The timing sequence function generates a continuously variable timing signal stream, while the random timing signal function produces random signals with uniformly distributed time intervals. Experimental results, using a Xilinx Kintex-7 FPGA, validate the effectiveness of the proposed methodology. The system achieves a resolution of 100 ps, a dynamic range from 1 ns to 40 {\mu}s, a DNL of -0.02/0.02 LSB, an INL of -0.04/0.03 LSB across the entire range. This approach can be readily adapted to various high-precision timing signal applications.