HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

TL;DR

HiVeGen is a hierarchical LLM-based framework for Verilog generation that improves complex hardware design accuracy by decomposing tasks, enabling design exploration, code reuse, and interactive correction.

Contribution

It introduces a hierarchical approach to HDL generation with integrated design exploration, code reuse, and human interaction, addressing hallucination issues in complex designs.

Findings

Enhanced accuracy in complex hardware designs

Effective code reuse through weight-based retrieval

Reduced error correction via real-time human interaction

Abstract

With Large Language Models (LLMs) recently demonstrating impressive proficiency in code generation, it is promising to extend their abilities to Hardware Description Language (HDL). However, LLMs tend to generate single HDL code blocks rather than hierarchical structures for hardware designs, leading to hallucinations, particularly in complex designs like Domain-Specific Accelerators (DSAs). To address this, we propose HiVeGen, a hierarchical LLM-based Verilog generation framework that decomposes generation tasks into LLM-manageable hierarchical submodules. HiVeGen further harnesses the advantages of such hierarchical structures by integrating automatic Design Space Exploration (DSE) into hierarchy-aware prompt generation, introducing weight-based retrieval to enhance code reuse, and enabling real-time human-computer interaction to lower error-correction cost, significantly improving the quality of generated designs.