The Tiny Median Filter: A Small Size, Flexible Arbitrary Percentile Finder Scheme Suitable for FPGA Implementation

TL;DR

The paper introduces the Tiny Median Filter, a compact, flexible, and resource-efficient scheme for arbitrary percentile filtering suitable for FPGA implementation, applicable to image processing and data analysis.

Contribution

It presents a novel small silicon resource-efficient design for an arbitrary percentile finder that can be used in various applications including image processing.

Findings

Low silicon resource usage

High operational frequency on FPGA

Flexible for various percentile and data set sizes

Abstract

This document reports the design, implementation and testing of a small silicon resource usage, very flexible arbitrary percentile finding scheme called the Tiny Median Filter. It can be used not only as a median filter in image processing with square filtering windows, but also for applications of any percentile filter or maximum or minimum finder with any size of data set as long as the number of bits of the data is finite. It opens possibilities for image processing tasks with non-square or irregular filter windows. In this scheme, data swapping or data bit manipulating are avoided and high functional efficiency of the logic components is applied to save silicon resources. Some logic functions are absorbed into other functions to further reduce the complexity. The combinational logic paths are designed to be sufficiently short so that the firmware can be compiled to the maximum operating frequency allowed by the block memories of the FPGA devices. The Tiny Median Filter receives, processes and output data in non-stop manner with no irregular timing which helps to simplify design of surrounding stages.