RISC-V Word-Size Modular Instructions for Residue Number Systems

TL;DR

This paper demonstrates that specialized RISC-V instructions for word-size modular arithmetic significantly accelerate Residue Number System computations, especially in cryptographic and digital signal processing applications, compared to traditional architectures.

Contribution

It introduces RISC-V instructions tailored for RNS modular arithmetic and evaluates their performance benefits through simulations and algorithm comparisons.

Findings

RNS modular multiplication with Kawamura's base extension is 2.76 times faster on In Order processors.

It is over 3 times faster on Out of Order processors.

Using specific instructions reduces cycle counts by 4.5x in In Order and 8x in Out of Order architectures.

Abstract

Residue Number Systems (RNS) are parallel number systems that allow the computation on large numbers. They are used in high performance digital signal processing devices and cryptographic applications. However, the rigidity of instruction set architectures of the market-dominant microprocessors limits the use of such number systems in software applications. This article presents the impact of word-size modular arithmetic specific RISC-V instructions on the software implementation of Residue Number Systems. We evaluate this impact on several RNS modular multiplication sequential algorithms. We observe that the fastest implementation uses the Kawamura et. al. base extension. Simulations of architectures with GEM5 simulator show that RNS modular multiplication with Kawamura's base extension is 2.76 times faster using specific word-size modular arithmetic instructions than pseudo-Mersenne moduli for In Order processors. It is more than 3 times for Out of Order processors. Compared to x86 architectures, RISC-V simulations show that using specific instructions requires 4.5 times less cycles in In Order processors and 8 less in Out of Order ones.