Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM

TL;DR

This paper offers practical verification strategies for complex hardware algorithms using UVM, emphasizing early bug detection through known-answer-tests and design-for-verification modes, based on real project experiences.

Contribution

It introduces pragmatic verification solutions leveraging UVM and known-answer-tests, tailored for complex mathematical hardware algorithms, with demonstrated effectiveness in real-world radar sensor projects.

Findings

Early bug detection through known-answer-tests

Effective verification of complex algorithms in hardware

Successful application in radar sensor projects

Abstract

This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner. Maximizing leverage of a known-answer-test strategy, based on predefined data scenarios combined with design-for-verification modes, we demonstrate how to find and isolate concept and design bugs early in the flow. The solutions presented are based on real project experience with single chip radar sensors for a variety of applications. The verification environments supporting the presented strategies are based on SystemVerilog and the Universal Verification Methodology.