Ultralow Voltage Operation of p- and n-FETs Enabled by Self-Formed Gate Dielectric and Metal Contacts on 2D Tellurium

TL;DR

This paper demonstrates ultralow voltage operation of 2D tellurium FETs by creating self-formed gate dielectrics and metal contacts, achieving record subthreshold slopes and low-voltage CMOS inverters for energy-efficient electronics.

Contribution

It introduces a novel fabrication approach for 2D tellurium transistors with self-formed gate dielectrics and transparent contacts, enabling ultralow voltage operation and high-performance CMOS circuits.

Findings

Record-low subthreshold slope of 3.5 mV/dec at 10 K

Ultralow voltage CMOS inverters operate at 0.08 V

High transparency and low contact resistance achieved

Abstract

The ongoing demand for more energy-efficient, high-performance electronics is driving the exploration of innovative materials and device architectures, where interfaces play a crucial role due to the continuous downscaling of device dimensions. Tellurium (Te), in its two-dimensional (2D) form, offers significant potential due to its high carrier mobility and ambipolar characteristics, with the carrier type easily tunable via surface modulation. In this study, we leverage atomically controlled material transformations in 2D Te to create intimate junctions, enabling near-ideal field-effect transistors (FETs) for both n-type and p-type operation. A NiTex-Te contact provides highly transparent interfaces, resulting in low contact resistance, while the TiOx-Te gate dielectric forms an ultraclean interface with a capacitance equivalent to 0.88 nm equivalent oxide thickness (EOT), where the quantum capacitance of Te is observed. Subthreshold slopes (SS) approach the Boltzmann limit, with a record-low SS of 3.5 mV/dec achieved at 10 K. Furthermore, we demonstrate 2D Te-based complementary metal-oxide-semiconductor (CMOS) inverters operating at an ultralow voltage of 0.08 V with a voltage gain of 7.1 V/V. This work presents a promising approach to forming intimate dielectric/semiconductor and metal/semiconductor junctions for next-generation low-power electronic devices.