PrefixLLM: LLM-aided Prefix Circuit Design

TL;DR

This paper introduces PrefixLLM, a novel approach that leverages large language models to synthesize optimized prefix circuits for digital adders, achieving reductions in area while maintaining delay constraints.

Contribution

It transforms prefix circuit synthesis into a structured text generation problem and employs LLMs for automatic, accurate design space exploration.

Findings

Reduces circuit area by 3.70% compared to state-of-the-art.

Uses LLMs to generate valid structured representations of prefix circuits.

Introduces an iterative framework for circuit synthesis and optimization.

Abstract

Prefix circuits are fundamental components in digital adders, widely used in digital systems due to their efficiency in calculating carry signals. Synthesizing prefix circuits with minimized area and delay is crucial for enhancing the performance of modern computing systems. Recently, large language models (LLMs) have demonstrated a surprising ability to perform text generation tasks. We propose PrefixLLM, that leverages LLMs for prefix circuit synthesis. PrefixLLM transforms the prefix circuit synthesis task into a structured text generation problem, termed the Structured Prefix Circuit Representation (SPCR), and introduces an iterative framework to automatically and accurately generate valid SPCRs. We further present a design space exploration (DSE) framework that uses LLMs to iteratively search for area and delay optimized prefix circuits. Compared to state-of-the-art, PrefixLLM can reduce the area by 3.70% under the same delay constraint. This work highlights the use of LLMs in the synthesis of arithmetic circuits, which can be transformed into the structured text generation.