High-Quality Iterative Logic Compiler for In-Memory SIMD Computation with Tight Coupling of Synthesis and Scheduling

TL;DR

This paper introduces an iterative logic compiler for SIMD in-memory computing that tightly integrates synthesis and scheduling, resulting in more efficient instruction sequences with lower energy-delay products.

Contribution

It presents a novel iterative compiler approach that improves instruction quality by coupling synthesis and scheduling, outperforming existing methods.

Findings

Energy-delay products reduced by 18.0% on average

Better instruction sequences achieved compared to state-of-the-art

Effective problem-specific resubstitution enhances performance

Abstract

In-memory computing (IMC) with single instruction multiple data (SIMD) setup enables memory to perform operations on the stored data in parallel to achieve high throughput and energy saving. To instruct a SIMD IMC hardware to compute a function, a logic compiler is needed that involves two steps: logic synthesis and scheduling. Logic synthesis transforms the function into a netlist of supported operations. Scheduling determines the execution sequence and memory location of the operations and outputs the instruction sequence given to the hardware. In this work, we propose an iterative logic compiler with tight coupling of synthesis and scheduling to find high-quality instruction sequences. It is based on improving the critical sub-netlist identified by our algorithm and performing problem-specific resubstitution. The experimental results show that our compiler can obtain better instruction sequences with energy-delay products reduced by 18.0% on average compared to the best state-of-the-art method.