Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic

TL;DR

This paper introduces a novel bipartitioned hybrid adder combining carry-select and carry-lookahead logic, achieving significant improvements in speed, area, and power efficiency over existing high-speed adders.

Contribution

The paper proposes a new FBHA design that integrates carry-lookahead and carry-select logic, demonstrating substantial performance and efficiency gains in 32-bit addition.

Findings

19.8% delay reduction over carry-lookahead adder

24.4% area reduction compared to carry-select adder

46.5% area reduction compared to Kogge-Stone adder

Abstract

We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a significant part and a less significant part joined together by a carry signal. In an N-bit FBHA, the K-bit less significant part is realized using carry-lookahead adder logic, and the (N-K)-bit significant part is realized using carry-select adder logic. The 32-bit addition was considered as an example operation for this work. Many 32-bit adders ranging from the slow ripple carry adder to the fast parallel-prefix Kogge-Stone adder and the proposed adder were synthesized using a 28-nm CMOS standard cell library and their design metrics were compared. A well-optimized FBHA achieved significant optimizations in design metrics compared to its high-speed adder counterparts and some examples are mentioned as follows: (a) 19.8% reduction in delay compared to a carry-lookahead adder; (b) 19.8% reduction in delay, 24.4% reduction in area, and 19.4% reduction in power compared to a carry-select adder; (c) 45.6% reduction in delay, and 13.5% reduction in power compared to a conditional sum adder; and (d) 46.5% reduction in area, and 29.3% reduction in power compared to the Kogge-Stone adder.