Controller-decoder system requirements derived by implementing Shor's algorithm with surface code

TL;DR

This paper identifies critical system-level requirements for controller-decoder systems to successfully implement non-Clifford quantum circuits, specifically Shor's algorithm, using surface code error correction on superconducting qubits.

Contribution

It provides a detailed analysis of the latency, communication, and hardware requirements for controller-decoder systems in fault-tolerant quantum computing with surface codes.

Findings

Controller-decoder latency must be within tens of microseconds.

Distributed decoding improves system performance.

Hardware with 0.1% error rates and 1000 qubits is sufficient for near-term implementations.

Abstract

Quantum Error Correction (QEC) is regarded as the most promising path to quantum advantage. The success of QEC relies on achieving quantum gate fidelities below the error threshold of the QEC code, while accurately decoding errors through classical processing of the QEC stabilizer measurements. In this paper, we uncover the critical system-level requirements from a controller-decoder system (CDS) necessary to successfully execute the next milestone in QEC: a non-Clifford circuit. Using a representative non-Clifford circuit, of Shor factorization algorithm for the number 21, we convert the logical-level circuit to a QEC surface code circuit and finally to the physical level circuit. By taking into account realistic implementation aspects using typical superconducting qubit processor parameters, we reveal a broad range of core requirements from any CDS aimed at performing error corrected quantum computation. Our findings indicate that the controller-decoder closed-loop latency must remain within tens of microseconds, achievable by distributing decoding data into several decoders while ensuring fast communication between decoders and with the controller. By extending existing simulation techniques, we simulate the complete fault-tolerant factorization circuit at the physical level, demonstrating that near-term hardware performance in the scale of 0.1% physical error rates and 1000 qubits, are sufficient for a successful circuit execution. Overall, the requirements outlined here set the stage for near- and medium-term experimental realizations of non-Clifford QEC circuits.