Leveraging Hardware Power through Optimal Pulse Profiling for Each Qubit Pair

TL;DR

This paper introduces a fine-grained, parallel calibration protocol for two-qubit gates in quantum computers, optimizing pulse waveforms per qubit pair, significantly reducing errors and increasing quantum volume.

Contribution

It proposes enlarging pulse options and a new calibration protocol with parallelization, improving calibration accuracy and hardware utilization in quantum devices.

Findings

Minimum gate error of 0.001 achieved

Median error reduced by 1.84x

Quantum volume doubled

Abstract

In the scaling development of quantum computers, the calibration process emerges as a critical challenge. Existing calibration methods, utilizing the same pulse waveform for two-qubit gates across the device, overlook hardware differences among physical qubits and lack efficient parallel calibration. In this paper, we enlarge the pulse candidates for two-qubit gates to three pulse waveforms, and introduce a fine-grained calibration protocol. In the calibration protocol, three policies are proposed to profile each qubit pair with its optimal pulse waveform. Afterwards, calibration subgraphs are introduced to enable parallel calibraton through identifying compatible calibration operations. The protocol is validated on real machine with up to 127 qubits. Real-machine experiments demonstrates a minimum gate error of 0.001 with a median error of 0.006 which is 1.84x reduction compared to default pulse waveform provided by IBM. On device level, a double fold increase in quantum volume as well as 2.3x reduction in error per layered gate are achieved. The proposed protocol leverages the potential current hardware and could server as an important step toward fault-tolerant quantum computing.